1. Field of the Invention
The present invention relates to a signal line drive circuit in an active matrix display device such as liquid crystal display device, display device and electronic apparatus.
2. Description of the Related Art
An image display device such as liquid crystal display device has a number of pixels arranged in a matrix form and displays an image by controlling the light intensity of each of the display cells (pixels) according to image information to be displayed.
Recent years have seen remarkable development of liquid crystal display devices and remarkable progress in their performance. Such display devices are applicable to electronic apparatuses designed to display an image or video of a video signal externally fed to or generated inside the electronic apparatus. Among examples of such electronic apparatus are television sets, mobile terminals such as mobile phones and PDAs (Personal Digital Assistants), digital cameras, laptop personal computers and video camcorders.
FIG. 1 is a diagram illustrating a rough configuration of a common liquid crystal display device.
A liquid crystal display device 1 includes an effective display section 2. The same section 2 includes a plurality of pixels, each having a liquid crystal cell, arranged in a matrix form on a transparent insulating substrate such as a glass substrate as illustrated in FIG. 1.
The liquid crystal display device 1 also includes a signal line drive circuit (horizontal drive circuit or source driver: HDRV) 3 adapted to drive signal lines and a gate line drive circuit (vertical drive circuit or gate driver: VDRV) 4.
The effective display section 2 includes a plurality of pixels, each having an unshown liquid crystal cell, arranged in a matrix form.
Further, the same section 2 includes signal lines and gate lines (vertical scan lines) disposed in a matrix form. The signal lines and gate lines are driven by the signal line drive circuit 3 and gate line drive circuit 4, respectively.
In a liquid crystal display device, an AC voltage must be applied to the liquid crystal to prevent degradation of the liquid crystal molecules. In a common crystal display device, a so-called polarity inversion method based on either common constant driving or common reversed driving is used in which an AC voltage (common voltage) is applied to the liquid crystal.
The common constant driving alternately applies two voltages, one positive and another negative, relative to the opposed electrode voltage, to the pixel electrode while at the same time maintaining the opposed electrode voltage constant.
The common reversed driving alternately applies two voltages, one positive and another negative relative to the opposed electrode voltage, to the pixel electrode while at the same reversing the opposed electrode voltage between high and low levels.
In this case, when the opposed electrode voltage is at high level, a negative voltage relative to this high level is applied to the pixel electrode. When the opposed electrode voltage is at low level, a positive voltage relative to this low level is applied to the pixel electrode.
The signal line drive circuit 3 is configured to handle this polarity reversal.
A multi-channel driver is commonly available for use in the signal line drive circuit 3 (refer to Japanese Patent Laid-Open No. Hei 9-26765).
Further, the signal line drive circuit 3 uses analog buffers with rail-to-rail outputs in its output buffer section (refer to CMOS Circuit Design, Layout and Simulation P661 FIG. 25. 49, R. Jacob, Baker Harry, W. LI David E. Boyce) or output selectors with switches (refer to Japanese Patent Laid-Open No. Hei 10-153986) to achieve polarity reversal.
FIG. 2 is a block diagram illustrating a configuration example of a common signal line drive circuit using output selectors.
The signal line drive circuit 3 includes a line buffer (LB) 31 and level shifter (LS) 32. The line buffer 31 stores drive data adapted to drive the signal lines. The level shifter 32 changes the data level of the line buffer 31 to a level commensurate with the drive level.
The same circuit 3 further includes a positive voltage supply section 36P and negative voltage supply section 36N each using a resistor string.
The signal line drive circuit 3 still further includes a selector section 33. The selector section 33 includes a plurality of digital/analog converters (DACs) adapted to receive positive and negative gray level voltages and convert digital drive data into analog data. The selector section 33 includes positive and negative selectors 33P and 33N.
The signal line drive circuit 3 still further includes a buffer amplifier section 34. The buffer amplifier section 34 amplifies the drive data output from the selector section 33 to generate positive and negative signal voltages. The same section 34 includes positive and negative buffer amplifiers 34P and 34N.
The signal line drive circuit 3 still further includes output selectors 35. Each of the output selectors 35 selectively switches signal voltages between positive and negative levels and supplies the voltages to signal lines adjacent to each other.
There is not much literature about the component layout of a multi-channel signal line drive circuit as shown in the block diagram of FIG. 2. In general, however, the circuit components are laid out in the same manner as in the block diagram.
FIG. 3 is a diagram illustrating the component layout of a common four-channel signal line drive circuit unit.
For example, in order to lay out the components of a four-channel (Ch) unit 40 as illustrated in FIG. 3, the line buffers 31 adapted to distribute digital signals of different channels are arranged first, followed by the level shifters 32.
Next, a positive selector 33P-1, negative selectors 33N-1 and 33N-2 and a positive selector 33P-2 are arranged in this order from left to right as illustrated in FIG. 3.
Next, a combined circuit 34PN is arranged which is a combination of the positive and negative buffer amplifiers 34P and 34N. Finally, the output selectors 35 are arranged that are adapted to switch the signals between positive and negative levels. The output wires from the output selectors are extended to the output pads of the respective channels.